? semiconductor components industries, llc, 2013 december, 2013 ? rev. 0 1 publication order number: ndd60n745u1/d ndd60n745u1 n-channel power mosfet 600 v, 745 m features ? 100% avalanche tested ? these devices are pb-free, halogen free/bfr free and are rohs compliant absolute maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain ? to ? source voltage v dss 600 v gate ? to ? source voltage v gs 25 v continuous drain current r jc steady state t c = 25 c i d 6.6 a t c = 100 c 4.2 power dissipation ? r jc steady state t c = 25 c p d 84 w pulsed drain current t p = 10 s i dm 27 a operating junction and storage temperature t j , t stg ? 55 to +150 c source current (body diode) i s 6.6 a single pulse drain ? to ? source avalanche energy (i d = 2.5 a) eas 38 mj peak diode recovery (note 1) dv/dt 15 v/ns lead temperature for soldering leads t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. i sd < 6.6 a, di/dt 400 a/ s, v ds peak v (br)dss , v dd = 80% v (br)dss thermal resistance parameter symbol value unit junction ? to ? case (drain) ndd60n745u1 r jc 1.5 c/w junction ? to ? ambient steady state (note 3) ndd60n745u1 (note 2) ndd60n745u1 ? 1 (note 2) ndd60n745u1 ? 35 r ja 47 98 95 c/w 2. insertion mounted 3. surface mounted on fr4 board using 1 sq. pad size (cu area = 1.127 in sq [2 oz] including traces) http://onsemi.com see detailed ordering and shipping information on page 3 of this data sheet. ordering information v (br)dss r ds(on) max 600 v 745 m @ 10 v n ? channel mosfet d (2) s (3) g (1) 1 2 3 4 ipak case 369d style 2 dpak case 369c style 2 1 2 3 4 ipak case 369ad style 2 1 2 3 4
ndd60n745u1 http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise noted) characteristic symbol test conditions min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs =0v, i d =1ma 600 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss /t j 540 mv/ c drain ? to ? source leakage current i dss v ds = 600 v, v gs =0v t j =25 c 1 a t j = 125 c 100 gate ? to ? source leakage current i gss v gs = 20 v 100 na on characteristics (note 4) gate threshold voltage v gs(th) v ds =v gs , i d = 250 a 2 3.2 4 v negative threshold temperature co- efficient v gs(th) /t j reference to 25 c, i d = 250 a 7.6 mv/ c static drain-to-source on resistance r ds(on) v gs =10v, i d = 3.25 a 610 745 m forward transconductance g fs v ds =15v, i d = 3.25 a 5.6 s dynamic characteristics input capacitance c iss v ds =50v, v gs = 0 v, f = 1 mhz 440 pf output capacitance c oss 27 reverse transfer capacitance c rss 1.5 effective output capacitance, energy related (note 6) c o(er) v gs = 0 v, v ds = 0 to 480 v 21 effective output capacitance, time related (note 7) c o(tr) i d = constant, v gs = 0 v, v ds = 0 to 480 v 71 total gate charge q g v ds = 300 v, i d = 6.8 a, v gs =10v 15 nc gate-to-source charge q gs 2.9 gate-to-drain charge q gd 7.3 plateau voltage v gp 5.3 v gate resistance r g 4.4 resistive switching characteristics (note 5) turn-on delay time t d(on) v dd = 300 v, i d = 6.8 a, v gs =10v, r g = 0 8 ns rise time t r 10 turn-off delay time t d(off) 19 fall time t f 7 source ? drain diode characteristics diode forward voltage v sd i s = 6.6 a, v gs =0v t j =25 c 0.90 1.6 v t j = 100 c 0.82 reverse recovery time t rr v gs =0v, v dd =30v i s = 6.8 a, d i /d t = 100 a/ s 260 ns charge time t a 130 discharge time t b 130 reverse recovery charge q rr 2.1 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. pulse width 300 s, duty cycle 2%. 5. switching characteristics are independent of operating junction temperatures. 6. c o(er) is a fixed capacitance that gives the same stored energy as c oss while v ds is rising from 0 to 80% v (br)dss 7. c o(tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v (br)dss
ndd60n745u1 http://onsemi.com 3 marking diagrams ipak ipak dpak y = year ww = work week g = pb ? free package 1 gate 2 drain 3 source 4 drain yww 60n 745u1g 4 drain 2 drain 1 gate 3 source yww 60n 745u1g 4 drain 1 gate 2 drain 3 source yww 60n 745u1g ordering information device package shipping ? ndd60n745u1 ? 1g ipak (pb-free, halogen-free) 75 units / rail ndd60n745u1 ? 35g ipak (pb-free, halogen-free) 75 units / rali ndd60n745u1t4g dpak (pb-free, halogen-free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ndd60n745u1 http://onsemi.com 4 typical characteristics figure 1. on ? region characteristics figure 2. transfer characteristics v ds , drain ? to ? source voltage (v) v gs , gate ? to ? source voltage (v) 30 25 20 15 10 5 0 0 2 8 12 14 10 8 6 4 3 2 0 4 6 12 14 figure 3. on ? resistance vs. gate ? to ? source voltage figure 4. on ? resistance vs. drain current and gate voltage i d , drain current (a) 8 4 2 0 0.5 1.4 0.6 0.7 0.8 0.9 1.0 1.5 figure 5. on ? resistance variation with temperature figure 6. breakdown voltage variation with temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ? 25 ? 50 0.4 0.6 1.0 1.2 1.6 1.8 2.2 2.6 125 100 75 50 25 0 ? 25 ? 50 0.925 0.950 0.975 1.000 1.050 1.075 1.100 1.125 i d , drain current (a) i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , normalized drain ? to ? source resistance bv dss , normalized breakdown voltage 4 v gs = 10 v to 6.5 v v gs , gate voltage (v) 10 9 8 7 6 5 4 0.5 0.6 0.7 0.8 0.9 1.3 1.5 r ds(on) , drain ? to ? source resistance ( ) t j = 25 c i d = 3.25 a 6 10 v gs = 6.0 v v gs = 5.5 v v gs = 5.0 v v gs = 4.5 v v gs = 4.0 v 2 8 10 v ds = 15 v t j = 150 c t j = 25 c t j = ? 55 c 6101214 t j = 25 c v gs = 10 v 150 0.8 1.4 2.0 2.4 i d = 3.25 a v gs = 10 v 150 1.025 i d = 250 a 579 1.0 1.1 1.2 1.4 1.1 1.2 1.3
ndd60n745u1 http://onsemi.com 5 typical characteristics figure 7. threshold voltage variation with temperature figure 8. drain ? to ? source leakage current vs. voltage t j , junction temperature ( c) v ds , drain ? to ? source voltage (v) 125 100 75 50 25 0 ? 25 ? 50 0.70 0.80 0.85 0.90 1.00 1.10 1.15 600 500 400 300 200 100 0 1 100 1000 10,000 figure 9. capacitance variation figure 10. gate ? to ? source and drain ? to ? source voltage vs. total charge v ds , drain ? to ? source voltage (v) q g , total gate charge (nc) 1000 100 10 1 0.1 1 10 100 1000 10,000 12 10 8 6 4 2 0 0 2 4 6 8 10 12 figure 11. resistive switching time variation vs. gate resistance figure 12. diode forward voltage vs. current r g , gate resistance ( ) v sd , source ? to ? drain voltage (v) 10 1 1 10 100 1000 1.1 0.9 0.6 0.4 0.1 1 10 100 v gs(th) , normalized threshold voltage i dss , leakage (na) c, capacitance (pf) v gs , gate ? to ? source voltage (v) t, time (ns) i s , source current (a) i d = 250 a 150 0.75 0.95 1.05 t j = 150 c t j = 100 c t j = 125 c v gs = 0 v t j = 25 c f = 1 mhz c oss c iss c rss v ds = 300 v t j = 25 c i d = 6.8 a 0 50 100 150 200 250 300 350 v ds , drain ? to ? source voltage (v) q t q gs q gd v ds v gs t j = 150 c t j = 100 c t j = 125 c t j = 25 c t d(on) t d(off) t r t f 100 16 14 1 3 5 7 9 11 v gs = 10 v v dd = 300 v i d = 6.8 a t j = ? 55 c 0.5 0.7 0.8 1.0 10
ndd60n745u1 http://onsemi.com 6 typical characteristics figure 13. maximum rated forward biased safe operating area v ds , drain ? to ? source voltage (v) 1000 100 10 1 0.1 0.01 0.1 1 10 100 figure 14. thermal impedance (junction ? to ? case) t, time (s) 1e ? 03 1e ? 01 1e ? 04 1e+00 1e ? 05 1e ? 02 1e ? 06 0.01 0.1 1 10 i d , drain current (a) r(t), effective transient thermal response ( c/w) 1e+01 1e+02 1e+03 single pulse duty cycle = 0.5 0.20 0.10 0.05 0.02 0.01 r jc steady state = 1.5 c/w v gs 25 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 10 s 100 s 1 ms 10 ms dc
ndd60n745u1 http://onsemi.com 7 package dimensions 123 4 v s a k ? t ? seating plane r b f g d 3 pl m 0.13 (0.005) t c e j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.35 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.045 0.94 1.14 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.350 0.380 8.89 9.65 r 0.180 0.215 4.45 5.45 s 0.025 0.040 0.63 1.01 v 0.035 0.050 0.89 1.27 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. z z 0.155 ??? 3.93 ??? ipak case 369d ? 01 issue c style 2: pin 1. gate 2. drain 3. source 4. drain 3.5 mm ipak, straight lead case 369ad issue b b d l e e3 l2 b1 e 3x a1 a a1 a2 dim min max millimeters a 2.19 2.38 a1 0.46 0.60 a2 0.87 1.10 b 0.69 0.89 b1 0.77 1.10 d 5.97 6.22 e 2.28 bsc d2 4.80 ??? e 6.35 6.73 e2 4.57 5.45 e3 4.45 5.46 l 3.40 3.60 l1 ??? 2.10 notes: 1.. dimensioning and tolerancing per asme y14.5m, 1994. 2.. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal tip. 4. dimensions d and e do not include mold gate or mold flash. t seating d2 e2 optional construction plane l1 l2 0.89 1.27 2x m 0.13 t d2 e2 style 2: pin 1. gate 2. drain 3. source 4. drain
ndd60n745u1 http://onsemi.com 8 package dimensions dpak (single gauge) case 369c issue d b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ndd60n745u1/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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